Etch stop layer formation in metal gate process

ABSTRACT

A method of forming a semiconductor device that includes forming a metal gate conductor of a gate structure on a channel portion of a semiconductor substrate. A gate dielectric cap is formed on the metal gate conductor. The gate dielectric cap is a silicon oxide that is catalyzed by a metal element from the gate conductor so that edges of the gate dielectric cap are aligned with a sidewall of the metal gate conductor. Contacts are then formed to at least one of a source region and a drain region that are on opposing sides of the gate structure, wherein the gate dielectric cap obstructs the contacts from contacting the metal gate conductor.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/449,433, filed Apr. 18, 2012 the entire content and disclosure ofwhich is incorporated herein by reference.

BACKGROUND

The present disclosure relates generally to semiconductor integratedcircuits. More particularly, the present disclosure relates to scalingof semiconductor devices, such as metal oxide semiconductor field effecttransistors (MOSFETs). In order to be able to make integrated circuits,such as memory, logic, and other devices, of higher integration densitythan currently feasible, one has to find ways to further downscale thedimensions of field effect transistors (FETs), such as MOSFETs andcomplementary metal oxide semiconductors (CMOS). Scaling achievescompactness and improves operating performance in devices by shrinkingthe overall dimensions of the device.

SUMMARY

In one embodiment, a semiconductor device is formed by a method thatincludes forming a metal gate conductor of a gate structure on a channelportion of a semiconductor substrate, wherein the metal gate conductoris comprised of a catalytic metal. A gate dielectric cap comprising atleast silicon and oxygen is formed on the metal gate conductor. The gatedielectric cap is catalyzed by the catalytic metal so that edges of thegate dielectric cap are aligned with a sidewall of the metal gateconductor. Contacts are then formed to at least one of a source regionand a drain region that are on opposing sides of the gate structure,wherein the gate dielectric cap obstructs the contacts from contactingthe metal gate conductor.

In another aspect, a semiconductor device is provided that includes agate structure on a channel portion of a semiconductor substrate. Thegate structure includes at least one gate dielectric in contact with thechannel portion of the semiconductor substrate and a gate conductorcomprised of a catalytic metal. The at least one gate dielectric has aU-shaped geometry. A gate dielectric cap is present on the gateconductor, wherein the gate dielectric cap has edges that aresubstantially self-aligned to sidewalls of the gate conductor. The gatedielectric cap comprises at least silicon and oxygen and has aself-limited thickness of less than 20 nm. A source region and a drainregion are present on opposing sides of the gate structure. A contact ispresent to each of the source region and the drain region. The contactis separated from the gate conductor by at least the gate conductor.

DESCRIPTION OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the disclosure solely thereto, will best beappreciated in conjunction with the accompanying drawings, wherein likereference numerals denote like elements and parts, in which:

FIG. 1 is a side cross-sectional view depicting one embodiment of aninitial structure of the disclosed method including a replacement gatestructure on a semiconductor substrate, a source region and a drainregion present in the semiconductor substrate on opposing sides of thesacrificial gate structure, and a spacer adjacent to the sacrificialgate structure, in accordance with the present disclosure.

FIG. 2 is a side cross-sectional view depicting one embodiment ofremoving the replacement gate structure to provide an opening to achannel portion of the semiconductor substrate, and forming a functionalgate structure in the opening, wherein the functional gate structureincludes at least one gate dielectric and at least one gate conductor.

FIG. 3 is a side cross-sectional view depicting one embodiment offorming a gate dielectric cap on the metal gate conductor, wherein thegate dielectric cap is a silicon oxide, or doped silicon oxide, withdopants being carbon, nitrogen, hydrogen or combined mixtures that iscatalyzed by a metal element from the catalytic metal so that edges ofthe gate dielectric cap are aligned with a sidewall of the metal gateconductor.

FIG. 4 is a side cross-sectional view depicting one embodiment offorming a contact to the source and drain regions of the semiconductordevice.

DETAILED DESCRIPTION

Detailed embodiments of the methods and structures of the presentdisclosure are described herein; however, it is to be understood thatthe disclosed embodiments are merely illustrative of the disclosedmethods and structures that may be embodied in various forms. Inaddition, each of the examples given in connection with the variousembodiments of the disclosure are intended to be illustrative, and notrestrictive. Further, the figures are not necessarily to scale, somefeatures may be exaggerated to show details of particular components.Therefore, specific structural and functional details disclosed hereinare not to be interpreted as limiting, but merely as a representativebasis for teaching one skilled in the art to variously employ themethods and structures of the present disclosure. For purposes of thedescription hereinafter, the terms “upper”, “lower”, “top”, “bottom”,and derivatives thereof shall relate to the disclosed structures, asthey are oriented in the drawing figures.

It has been determined that one consequence of scaling semiconductordevices, such as field effect transistors (FETs), is that as thedistance between adjacent semiconductor devices is decreased it isbecomes increasingly difficult to form interconnects to the sourceregion and the drain region without shorting the gate structures. In oneaspect, the present disclosure provides a process sequence formanufacturing a semiconductor device that forms a dielectric gate capatop a metal gate conductor composed of a catalytic metal, in which thecatalytic metal functions as a catalyst to selective deposition of thedielectric material of the dielectric gate cap on only the metal gateconductor in a self-aligned manner. More specifically, by self-alignedit is meant that the deposited material of the dielectric gate cap isdeposited continuously atop the entire upper surface of the metal gateconductor, wherein the edges of the dielectric gate cap are aligned tothe sidewalls of the metal gate conductor. In one embodiment, thecatalytic metal that dictates the self-aligned characteristics of thedielectric gate cap also provides that the dielectric gate cap has aself-limiting thickness.

FIG. 1 illustrates the results of initial processing steps of thepresent disclosure that produce a replacement gate structure 10 on asemiconductor substrate 5 including a source region 20 and a drainregion 25 present in the semiconductor substrate 5 on opposing sides ofthe replacement gate structure 10, at least one dielectric spacer 15adjacent to the replacement gate structure 10, and an interleveldielectric layer 30 adjoining the replacement gate structure 10 andlocated on the exposed surface of the semiconductor substrate 5. Thesemiconductor substrate 5 may be composed of a silicon containingmaterial. Silicon containing materials include, but are not limited to,Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicongermanium, polycrystalline silicon germanium, or silicon doped withcarbon, amorphous Si and combinations and multi-layers thereof. Thesemiconductor substrate 5 may also be composed of other semiconductormaterials, such as germanium, and compound semiconductor substrates,such as type III/V semiconductor substrates, e.g., GaAs. Although thesemiconductor substrate 5 is depicted as a bulk semiconductor substrate,semiconductor on insulator (SOI) substrate arrangements, such as siliconon insulator substrates, are also suitable for the semiconductorsubstrate 5.

Still referring to FIG. 1, the replacement gate structure 10 is formedon the channel portion of the semiconductor substrate 5. As used herein,the term “replacement gate structure 10” denotes a sacrificial structurethat dictates the geometry and location of the later formed functioninggate structure. The functional gate structure controls output current,i.e., flow of carriers in the channel region of the semiconductordevice. The channel region is the region between the source region andthe drain region of the semiconductor device that becomes conductivewhen the transistor is turned on. The sacrificial material that providesthe replacement gate structure 10 may be composed of any material thatcan be etched selectively to the bottom dielectric films orsemiconductor substrate 5. In one embodiment, the sacrificial materialthat provides the replacement gate structure 10 may be composed of asilicon-containing material, such as polysilicon. Although, thereplacement gate structure 10 is typically composed of a semiconductormaterial, the replacement gate structure 10 may also be composed ofdoped Si layers with Ge, or a dielectric material, such as amorphouscarbon. The sacrificial material may be patterned and etched to providethe replacement gate structure 10. Specifically, and in one example, apattern is produced by applying a photoresist to the surface to beetched, exposing the photoresist to a pattern of radiation, and thendeveloping the pattern into the photoresist utilizing a resistdeveloper. Once the patterning of the photoresist is completed, thesections of the sacrificial material covered by the photoresist areprotected to provide the replacement gate structure 10, while theexposed regions are removed using a selective etching process thatremoves the unprotected regions. Following formation of the replacementgate structure 10, the photoresist may be removed.

At least one dielectric gate spacer 15 may then be formed adjacent tothe replacement gate structure 10, i.e., in direct contact with thesidewall of the replacement gate structure 10. In one embodiment, the atlast one dielectric gate spacer 15 may be formed by using a blanketlayer deposition, such as chemical vapor deposition, and an anisotropicetchback method. The at least one dielectric gate spacer 15 may have awidth ranging from 2.0 nm to 15.0 nm, and may be composed of adielectric, such as a nitride, oxide, oxynitride, or a combinationthereof. The dielectric gate spacer 15 is optional, and may be omitted.

In some embodiments, a source region 20 and a drain region 25 may thenbe formed in the portions of the semiconductor substrate 5 that arepresent on opposing sides of replacement gate structure 10. In oneembodiment, the source region 20 and the drain region 25 are formedusing an ion implantation process. The conductivity type, e.g., n-typeor p-type, of the source region 20 and the drain region 25 typicallydictates the conductivity type of the semiconductor device, e.g., nFETor pFET. In a silicon-containing semiconductor substrate 5, examples ofp-type dopants, i.e., impurities, include but are not limited to, boron,aluminum, gallium and indium, and examples of n-type dopants, i.e.,impurities, include but are not limited to antimony, arsenic andphosphorous.

Still referring to FIG. 1, in one embodiment, a first interleveldielectric layer 30 is formed atop the source region 20 and the drainregion 25, wherein the upper surface of the interlevel dielectric layer30 is coplanar with an upper surface of the replacement gate structure10. The composition of the first interlevel dielectric layer 30 may beselected from the group consisting of silicon-containing materials suchas SiO₂, Si₃N₄, SiO_(x)N_(y), SiC, SiCO, SiCOH, SiCBN and SiCHcompounds, the above-mentioned silicon-containing materials with some orall of the Si replaced by Ge, carbon-doped oxides, inorganic oxides,inorganic polymers, hybrid polymers, organic polymers such as polyamidesor SiLK™, other carbon-containing materials, organo-inorganic materialssuch as spin-on glasses and silsesquioxane-based materials, anddiamond-like carbon (DLC, also known as amorphous hydrogenated carbon,α-C:H). The first interlevel dielectric layer 30 may be formed using adeposition method such as chemical vapor deposition (CVD) or spin ondeposition. Following deposition the first interlevel dielectric layer30 may be planarized, e.g., planarized by chemical mechanicalplanarization (CMP), so that an upper surface of the first interleveldielectric layer 30 is coplanar with an upper surface of the replacementgate structure 10.

FIG. 2 depicts one embodiment of removing the replacement gate structure10 to provide an opening to a channel portion of the semiconductorsubstrate 5, and forming a functional gate structure 45 in the opening.The etch process for removing the replacement gate structure 10 may be aselective etch. As used herein, the term “selective” in reference to amaterial removal process denotes that the rate of material removal for afirst material is greater than the rate of removal for at least anothermaterial of the structure to which the material removal process is beingapplied. For example and in one embodiment, a selective etch may includean etch chemistry that removes a first material selectively to a secondmaterial by a ratio of 2:1 or greater, such as 5:1. The replacement gatestructure 10 may be removed using a wet or dry etch process, such asreactive ion etch (RIE), or combination of these techniques thereof. Inone example, an etch step for removing the replacement gate structure 10can include an etch chemistry for removing the replacement gatestructure 10 selective to the substrate dielectrics or semiconductorsubstrate 5.

Still referring to FIG. 2, the functional gate structure 45 includes atleast one gate dielectric 46 and at least one gate conductor 47. The atleast one gate dielectric 46 may be composed of any dielectric materialincluding oxides, nitrides and oxynitrides. In one embodiment, the atleast one gate dielectric 46 may be provided by a high-k dielectricmaterial. The term “high-k” as used to describe the material of the atleast one gate dielectric 46 denotes a dielectric material having adielectric constant greater than silicon oxide (SiO₂) at roomtemperature (20° C. to 25° C.) and atmospheric pressure (1 atm). Forexample, a high-k dielectric material may have a dielectric constantgreater than 4.0. In another example, the dielectric constant of thehigh-k dielectric material may be greater than 10.0. In one embodiment,the at least one gate dielectric 46 is composed of a high-k oxide suchas, for example, HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃and mixtures thereof.

In one embodiment, the at least one gate dielectric 46 may be depositedby chemical vapor deposition (CVD), such as plasma enhanced CVD (PECVD).In one embodiment, the at least one gate dielectric 46 may be depositedusing a conformal deposition method. The term “conformal” denotes alayer having a thickness that does not deviate from greater than or lessthan 20% of an average value for the thickness of the layer. In oneembodiment, the thickness of the at least one gate dielectric 46 rangesfrom 0.8 nm to 6.0 nm. In one embodiment, the side cross-section of atleast one gate dielectric 46 has a U-shaped geometry, as depicted inFIG. 2, in which a portion of the at least one gate dielectric 46extends along an entire height of the interior sidewalls of thedielectric spacer 15 and a portion of the at least one gate dielectric46 is present on the surface of the semiconductor substrate 5 thatincludes the device channel.

The at least one metal gate conductor 47 is formed on the at least onegate dielectric 46. The at least one metal gate conductor 47 is composedof a catalytic metal. A “catalytic metal” is a metal that provides for apolymerization reaction with the precursor of the atomic layerdeposition (ALD) half reaction for forming the gate dielectric cap thatis self-aligned to the metal gate conductor. In one embodiment, thecatalytic metal is a Lewis-acid type metal. As used herein, a“Lewis-acid type metal” is a metal ion that functions as an electronpair acceptor in the formation of a stable substance. Examples ofcatalytic metals include aluminum (Al), hafnium (Hf), zirconium (Zr),titanium (Ti), tantalum (Ta), tungsten (W) and a combination thereof.The at least one metal gate conductor 47 may be formed by a depositionprocess, such as CVD, plasma-assisted CVD, plating, and/or sputtering,followed by planarization. More specifically, in one embodiment, the atleast one metal gate conductor 47 may be deposited filling the openingproduced by removing the replacement gate structure 10.

FIG. 3 depicts one embodiment of forming a gate dielectric cap 50 on theat least one metal gate conductor 47, wherein the gate dielectric cap 50is a silicon and oxygen containing dielectric that is catalyzed by thecatalytic metal of the gate conductor 471 so that edges E1 of the gatedielectric cap 50 are substantially aligned with a sidewall of the atleast one metal gate conductor 47. By “substantially aligned” it is meanthat the sidewall of edge E1 of the gate dielectric cap 50 may extendfrom the sidewall of the at least one metal gate conductor 47 by adimension of 20 nm or less. The catalytic effect provided by thecatalytic metal means that there is substantially no deposition of thematerial for the gate dielectric cap 50 grown on the first interleveldielectric layer 30 and the semiconductor substrate. The material forthe gate dielectric cap 50 is only deposited on the upper surface of theat least one metal gate conductor 47 of the catalytic metal. Morespecifically, in some embodiments, the ALD half reaction depositionprocess, which will be described in more detail below, provides for aself limiting thickness of 20 nm or less. Therefore, because thematerial of the gate dielectric cap 50 can only extend from thecatalytic metal that provides the at least one metal gate conductor 47,the maximum amount of lateral growth of the gate dielectric cap 50 canbe 20 nm, which allows for some overlap of the dielectric spacers 15 orlateral extension to first interlevel dielectric layer 30. The materialof the gate dielectric cap 50 is not grown on an exterior surface of thefirst interlevel dielectric layer 30. The gate dielectric cap 50 mayprovide an etch stop layer to protect the at least one metal gateconductor 47 during subsequent etch steps to form vias to the sourceregion 20 and drain region 25, for the subsequently formed contacts;i.e., interconnects.

The gate dielectric cap 50 may be formed using an atomic layerdeposition (ALD) half reaction. Atomic Layer Deposition (ALD) usesself-limiting surface reactions to deposit material layers in themonolayer or sub-monolayer thickness regime. ALD is similar in chemistryto chemical vapor deposition (CVD), except that the ALD reaction breaksthe CVD reaction into two half-reactions, keeping the precursormaterials separate during the reaction. The atomic layer depsoition(ALD) process of the present disclosure uses only half reactions todeposit the gate dielectric cap 50. The precusor of the atomic layerdeposition process may be a silicon containing precursor. In someembodiments, the percursor may have the following chemical formulation:

In one embodiment, in which R in the above chemical formula is equal toan alkyloxy group, the precursor may be tris (tert-butyloxyl) silanol.In another embodiment, in which R in the above chemical formula is abutyl group, such as tert-butyl, the precursor may be at least one ofbis(tert-butyloxyl) alkyl silanol, and mono-tert-butyloxyl alkylsilanol. Other butyl groups that are suitable for R in the abovechemical formula include n-butyl, iso-butyl, and sec-butyl. It is notedthat the above examples are provided for illustrative purposes only, asthe R group in the above chemical formula for the precursor of the ALDhalf reaction may be any group having a carbon chain. For example, the Rgroup in the above chemical formula may be an alkyl group, such asmethyl group, ethyl group, propyl group, n-propyl group, isopropylgroup, pentyl group, hexyl group, octyl group and combinations thereof.

In one example, in which the silicon precursor of the ALD half reactionprocess is tris (tert-butyloxyl) silanol, the deposited gate dielectriccap 50 is composed of silicon oxide (SiO₂). In another example, in whichthe silicon precursor of the ALD half reaction process isbis(tert-butyloxyl) alkyl silanol, the deposited gate dielectric cap 50is silicon-oxycarbide (SiCO). In another example, in which the siliconprecursor of the ALD half reaction process isbis-tert-butyloxyl-aminoalkyl silanol, the gate dielectric cap 50comprises silicon carbon nitro-oxide (SiCNO).

The ALD half reaction using one of the above described precursors is aself-aligned and self-limiting deposition process. For example, in someembodiments, the above described precursor gasses are chemisorbed by thecatalytic metal of the at least one metal gate conductor 47, wherein thesilanol molecules can then diffuse into the catalytic metal. Repeatedinsertion of the silanol molecules into the catalytic metal of the atleast one metal gate conductor 47 form a siloxane polymer bound to thesurface of the at least one metal gate conductor 47 through thecatalytic metal, e.g., aluminum. This siloxane polymer is attached tothe surface by strong chemical bonds and is thus non-volatile, i.e., achemisorbed material. Because silanol can diffuse through this soft,surface bound siloxane polymer, the catalytic metal remains available tocatalyze the polymerization of the silanol molecules. The self-alignedand rate-limiting mechanism in this process is the catalytic conversionof silanol to siloxane, provided that the concentration of silanol vaporis sufficiently high to keep the catalytic aluminum atoms fullyoccupied. In this case, the chemisorption rate does not depend on therate at which silanol arrives at the surface of the siloxane layer. Inthe language of chemical kinetics, the chemisorption rate is zero orderin the vapor concentration of silanol. The self aligned andself-limiting nature of the ALD half reaction results from cross-linkingof the siloxane polymer.

More specifically, the cross-linking reactions connect the siloxanepolymer chains, causing the polymer layer to gel and eventuallysolidify. For example, in the embodiments in which the precursor of theALD half reaction is tris (tert-butyloxyl) silanol, the polymer layermay solidify to form silica (SiO₂). In another example, in which theprecursor of the ALD half reaction is bis(tert-butyloxyl) alkyl silanol,the polymer layer may solidify to form silicon-oxycarbide (SiCO). In yetanother example, in which the precursor of the ALD half reaction ismono-tert-butyloxyl alkyl silanol, the polymer layer may solidify toform silicon carbon nitro-oxide (SiCNO). Because the silanol presumablyhas a negligible rate of diffusion through solid silica,silicon-oxycarbide (SiCO) or silicon carbon nitro-oxide (SiCNO),additional silanol can no longer reach the catalytic metal, e.g.,aluminum, so the chemisorption stops, i.e., becomes self-limited. By“self-limiting” or “self-limited” it is meant that the amount of filmmaterial deposited in each reaction cycle of the ALD deposition isconstant. One ALD half reaction may take from 0.5 seconds to a fewseconds and may deposit a gate dielectric cap 50 having a self limitedthickness between 1.0 nm and 20 nm. In another embodiment, the gatedielectric cap 50 has a self limited thickness that ranges from 1.0 nmto 10 nm. The self-limited thickness may be provided by one ALD halfreaction cycle. Further details regarding one embodiment of the ALD halfreaction process that provides the self-aligned and self-limited gatedielectric cap 50 may be found in Hausmann et al. “Rapid VaporDeposition of Highly Conformal Silica Nanolaminates”, Science, Vol. 498,p. 402 (Oct. 11, 2002).

FIG. 4 depicts one embodiment of forming a contact 60 to the sourceregion 20 and the drain region 25 of the semiconductor device 100. Inone embodiment, a second interlevel dielectric layer 55 is depositedover the structure depicted in FIG. 3, and contacts 60 are formed to thesource regions 20 and drain regions 25 of the semiconductor device 100.The composition of the second interlevel dielectric layer 55 may besimilar to the first interlevel dielectric layer 30 that is describedabove with reference to FIG. 1. Therefore, the description of the firstinterlevel dielectric layer 30 that is described above with respect toFIG. 1 is suitable for the second interlevel dielectric layer 55 that isdepicted in FIG. 4.

Via openings may be formed to expose an upper surface of the sourceregion 20 and the drain region 25. The via openings may be formed usingphotolithography and etch processes. For example, a photoresist etchmask can be produced by applying a photoresist layer to the uppersurface of the second interlevel dielectric layer 55, exposing thephotoresist layer to a pattern of radiation, and then developing thepattern into the photoresist layer utilizing a resist developer. Thephotoresist etch mask may be positioned so that the portions of thesecond interlevel dielectric layer 55 that are not protected by thephotoresist etch mask may be etched in order to provide the viaopenings. The exposed portion of the second interlevel dielectric layer55 is then removed by a selective etch. The etch that removes theexposed portions of the second interlevel dielectric layer 55 isselective to at least the gate dielectric cap 50, and may also beselective to the dielectric spacers 15 and the semiconductor substrate5. The etch that removes the exposed portion of the second interleveldielectric layer 55 may be an anisotropic etch. Examples of anisotropicetch process suitable for forming the via openings include, but are notlimited to, reactive-ion etching (RIE), ion beam etching, plasma etchingand/or laser ablation. Contacts 60 may be formed in the via openings, inwhich the contacts 60 are in direct contact with the upper surface ofthe source region 20 and the drain region 25. Contacts 60 are formed bydepositing a conductive metal into the via openings using a depositionprocess, such as physical vapor deposition (PVD), such as sputtering andplating. The contact 60 may be composed of conductive metals, such astitanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper,manganese, aluminum, silver, gold, and alloys thereof. Following theformation of the contacts 60, a separate contact may be formed to the atleast one metal gate conductor 47.

Referring to FIG. 4, in one embodiment a semiconductor device 100 isprovided that includes a functional gate structure 45 on a channelportion of a semiconductor substrate 5. The gate structure 45 includesat least one gate dielectric 46 having a U-shaped geometry in contactwith the channel portion of the semiconductor substrate 5 and a metalgate conductor 47 comprised of a catalytic metal. The gate dielectriccap 50 has edges E1 that are self-aligned to sidewalls of the gateconductor 47. The gate dielectric cap 50 typically has a self-limitingthickness of less than 20 nm. In one embodiment, the gate dielectric cap50 has a thickness ranging from 1 nm to 15 nm. In one embodiment, aninterface oxide may be present between the gate dielectric cap 5 and thecatalytic metal of the metal gate conductor 47. The interface oxide 51includes a metal element from the catalytic metal. In one embodiment, inwhich the catalytic metal is composed of aluminum (Al), the interfaceoxide 51 is comprised of aluminum oxide (Al₂O₃).

Still referring to FIG. 4, the gate dielectric cap 50 protects the gateconductor 47 from being shorted to the source region 25 and the drainregion 30 by the contact 60, because the gate dielectric cap 50separates the contact 60 from the metal gate conductor 47. Therefore,the gate dielectric cap 50 prevents shorting between the contact 60 tothe source region 25 and the drain region 30 and the metal gateconductor 47 with increased scaling of the semiconductor device 100. Forexample, the methods and structures disclosed herein may be applicableto semiconductor devices 100, 110 separated by a pitch between adjacentgate structures 45, 45 a ranging from 30 nm to 100 nm.

While the claimed methods and structures has been particularly shown anddescribed with respect to preferred embodiments thereof, it will beunderstood by those skilled in the art that the foregoing and otherchanges in form and details may be made therein without departing fromthe spirit and scope of the presently claimed methods and structures.

What is claimed is:
 1. A semiconductor device comprising: a gatestructure on a channel portion of a semiconductor substrate, wherein thegate structure includes at least one gate dielectric layer having aU-shaped geometry in contact with the channel portion of thesemiconductor substrate and a metal gate conductor comprised of acatalytic metal; a gate dielectric cap having edges that aresubstantially self-aligned to sidewalls of the metal gate conductor,wherein the gate dielectric cap is an oxide-containing dielectric havinga self-limited thickness of less than 20 nm; a source region and a drainregion on opposing sides of the gate structure; and a contact to each ofthe source region and the drain region, wherein the contact is separatedfrom the metal gate conductor by at least the gate dielectric cap. 2.The semiconductor device of claim 1, wherein the at least one gatedielectric layer is comprised of a high-k dielectric material.
 3. Thesemiconductor device of claim 1, wherein the at least one gatedielectric layer has a thickness that ranges 0.8 mm to 6.0 mm.
 4. Thesemiconductor device of claim 2, wherein the high-k dielectric materialis selected from the group consisting of HfO₂, ZrO₂, Al₂O₃, TiO₂, La₂O₃,SrTiO₃, LaAlO₃, Y₂O₃ and mixtures thereof.
 5. The semiconductor deviceof claim 1, wherein the gate dielectric cap comprises at least one ofsilicon-oxycarbide (SiCO), silicon carbon nitro-oxide (SiCNO) andsilicon oxide (SiO₂).
 6. The semiconductor device of claim 1, whereinthe catalytic metal comprises aluminum (Al), hafnium (Hf), zirconium(Zr), titanium (Ti), tantalum (Ta), tungsten (W) or a combinationthereof.
 7. The semiconductor device of claim 1, wherein a spacer isadjacent to the gate structure.
 8. The semiconductor device of claim 4,wherein said edges of the gate dielectric cap that are substantiallyself-aligned to sidewalls of the metal gate conductor may extend pastthe metal gate conductor over the spacer by a dimension of 20 nm orless.
 9. The semiconductor device of claim 1, wherein the gate structureof the semiconductor device and an adjacent gate structure of anadjacent semiconductor device are separated by a pitch ranging from 30nm to 100 nm.
 10. The semiconductor device of claim 1 further comprisingdielectric spacers adjacent to the gate structure, wherein the materialof the gate dielectric cap is not present on an exterior surface of thedielectric spacers.
 11. The semiconductor device of claim 1, wherein thecatalytic metal is aluminum, the interface oxide is aluminum oxide(Al₂O₃), and the gate dielectric cap is silicon oxide (SiO₂).
 12. Thesemiconductor device of claim 1, wherein at least one contact of saidcontact to each of the source region and the drain region is in directcontact with the gate dielectric cap.
 13. The semiconductor device ofclaim 1, wherein the at least one contact is comprised oftitanium/titanium nitride/tungsten, tantalum nitride/tantalum/copper,manganese, aluminum, silver, gold, or alloys thereof.